Clock Report for Full_Adder


Rate Information

Model Base Rate	0.2
DUT Base Rate	0.2

Clock Enable Table

Clock Enable Name	Sample Time
	0.2

Output Signal Table

Output Signal	Clock Enable Name	Sample Time	Latency
P0		0.2	0
P1		0.2	0
P2		0.2	0
P3		0.2	0
P4		0.2	0
P5		0.2	0
P6		0.2	0
P7		0.2	0
P8		0.2	0
P9		0.2	0
P10		0.2	0
P11		0.2	0
P12		0.2	0
P13		0.2	0
P14		0.2	0
P15		0.2	0